1. Field of the Invention
The present invention relates to an input protection circuit for protecting an input circuit portion of an integrated circuit device such as CMOSIC from breakdown by electro-static discharge (ESD) or the like.
2. Description of the Related Art
A conventional input protection circuit used for CMOSIC or the like has a MOS transistor whose drain is connected to an input terminal of CMOSIC or the like and whose gate and source are connected to the ground potential. The gate insulating film of the MOS transistor of such an input protection circuit has a low breakdown voltage of about 10 V so that an ESD breakdown voltage is low.
An input protection circuit having a higher ESD breakdown voltage has been proposed such as shown in FIGS. 10 and 11. In FIGS. 10 and 11, reference characters IN represent an input terminal from which an input signal is supplied to a circuit to be protected.
In the circuit shown in FIG. 10, in one principal surface area of a p-type silicon substrate 1, a p-type well region 2 is formed in which n-type well regions 3 and 4 are formed. A MOS transistor is formed by the n-type well regions 3 and 4 and a channel made of a portion of the p-type well region 2. The bottoms of both the n-type well regions 3 and 4 form PN junctions with the substrate 1. In the well regions 3 and 4, n+-type impurity doped regions 5 and 6 are formed to provide contact regions, and in the p-type well region 2, a p+-type impurity doped region 7 is formed to provide a contact region.
On the principal surface of the substrate 1, a field insulating film 8 made of silicon oxide or the like is formed. On the insulating film 8 above the channel region between the well regions 3 and 4, a gate electrode layer 9 made of polysilicon or the like is formed. The impurity doped region 5 and gate electrode layer 9 are connected to the input terminal IN. The impurity doped regions 6 and 7 are both connected to the ground potential.
FIG. 11 is an equivalent circuit diagram of the integrated circuit structure shown in FIG. 10. The drain and gate (well region 3 and gate electrode layer 9 shown in FIG. 10) of an n-channel MOS type transistor FT are connected to the input terminal IN. The source (well region 4 shown in FIG. 10) of the transistor FT is connected to the ground potential. A diode D is formed between the well region 3 and substrate 1, the cathode and anode thereof being connected to the input terminal IN and ground potential, respectively. An NPN type lateral bipolar transistor BT is made of the well regions 3 and 4 and a p-type region (a portion of the well region 2) between the well regions 3 and 4, the collector and emitter thereof being connected to the input terminal IN and ground potential, respectively. Between the base and emitter of the transistor BT, a resistor R made of the resistance components of the substrate is connected. The well region 2 and substrate 1 are connected to the ground potential.
When an ESD input of +V is applied to the input terminal IN, the transistor FT turns on to protect a subject circuit CP to be protected. Since the thick field insulating film 8 is used as the gate insulating film of the transistor FT, it has a high ESD breakdown voltage. In this specification, the term “ESD input” is intended to mean “a surge voltage input caused by static electricity or the like”.
The diode D is made of a PN junction between well regions 3 and 2 and between the well region 3 and substrate 1 (i.e., PN junctions formed between low impurity concentration regions) so that it has a high inverse breakdown voltage of about 50 V. The level of a positive signal capable of being input to the subject circuit to be protected is limited by the inverse breakdown voltage of the diode D. When an ESD input of −V is applied to the input terminal IN, the diode D turns on to protect the subject circuit CP to be protected.
In the field of audio circuits, CMOSIC is generally required to process a signal in the range from +15 V to −15 V. With the conventional circuit described above, although a +15 V input signal can be processed, a −15 V input signal cannot be input because a negative input signal turns on the diode D.